NAND Flash

NAND flash is the storage medium that has displaced rotating disks as the dominant technology for personal storage. It’s inside every SSD, every USB drive, every SD card, every smartphone, every modern tablet, every modern game console, and most laptops. NAND flash is to SSDs what platters are to HDDs; it’s the actual physical thing where bits live.¹

A brief history

The eProvided NAND flash documentation captures the origin: “Fujio Masuoka at Toshiba in the 1980s” invented NAND flash, designed for “block-based access (operating more like a disk drive, ideal for mass storage).” The technology took several decades to mature into the dominant storage medium it is today; through the 1990s and 2000s, NAND was used primarily in low-capacity removable media (memory cards, USB drives) before scaling up to compete with HDDs in the SSD form factor through the 2010s and dominating storage by the 2020s.

NAND vs NOR flash

Two organizations of flash memory exist, both named after logic-gate topologies. The eProvided documentation captures the difference: NAND flash “is designed for block-based access (operating more like a disk drive, ideal for mass storage). NOR flash supports random access, functioning more like traditional memory for code execution.” NAND has “faster erase and write cycles, higher density, and ten times the endurance of NOR flash” but “I/O user interface allows only consecutive access to data, which makes it suitable for mass-storage devices and much less beneficial for computer memory.”

Modern systems typically use both: NOR flash for boot ROM and embedded firmware (where code execution matters more than capacity), NAND flash for user data storage (where capacity and cost matter more than random access). Mass storage scenarios are essentially always NAND.

Hierarchical structure of NAND memory

NAND memory is organized in a hierarchy that’s important for understanding both how it works and how it fails:

• Cell: the smallest unit; one floating-gate transistor that stores one or more bits.
• Page: the smallest read or write unit; typically 4 KB to 16 KB. Cells in a page share electrical pathways.
• Block: the smallest erase unit; typically hundreds of pages (a block might be 256 KB to several megabytes). Erase operations affect entire blocks.
• Plane: a group of blocks that can operate independently of other planes within the same die.
• Die: one silicon chip containing one or more planes.
• Package: one physical NAND chip, containing one or more dies.

An SSD typically contains many NAND packages working in parallel; the SSD controller distributes data across dies and planes to maximize throughput.

3D NAND / V-NAND

Through the early 2010s, NAND density increases came from shrinking cell size laterally (smaller features on a 2D wafer). Around 2013, the industry hit physical limits where further shrinking caused unacceptable error rates. The response was to stack cells vertically: 3D NAND (Samsung calls it V-NAND) builds 96, 128, 176, or even more layers of cells stacked on top of each other. Modern high-capacity NAND chips contain hundreds of stacked layers, allowing dramatic capacity growth without the per-cell shrinkage problem.

The basic storage mechanism is electrical charge trapped in a small region of an otherwise insulating structure. Reading the cell measures the trapped charge; writing changes it; erasing removes it. Several quirks of this mechanism shape everything about how SSDs work and how they fail.²

The floating-gate transistor

Each NAND cell is a transistor with a special “floating gate” embedded in the gate oxide. The floating gate is electrically isolated from the rest of the circuit; once charge is placed on it, that charge stays there essentially indefinitely (without power). To read the cell, the controller measures the threshold voltage at which the transistor conducts; the threshold depends on how much charge is on the floating gate. To write a cell, the controller applies a high voltage that drives electrons through the oxide to deposit charge on the floating gate. To erase a cell, the controller applies a different high voltage that drives electrons off the floating gate.

The “1 to 0 only” write rule

NAND has a fundamental architectural constraint: writes can only flip a bit from 1 (uncharged) to 0 (charged); flipping a bit from 0 back to 1 requires an erase operation. This is because the write process can only add charge to the floating gate, not remove it. Erasing removes charge from all cells in a block simultaneously, returning every bit in the block to 1.

This rule has profound consequences: SSDs cannot modify a single byte in place. To change one byte in a logical sector, the controller has to read the surrounding data, modify the byte, find a fresh erased block, write the modified data to the new block, and update its mapping table to point to the new block. The original block becomes “garbage” that’s eventually erased and reused. This is why SSDs need wear leveling, garbage collection, and over-provisioning to function efficiently.

The encoding of bit values

Different NAND types encode different numbers of bits per cell by using different amounts of trapped charge to represent different bit values:

• SLC: two distinct charge states (one charged, one uncharged) representing 0 and 1.
• MLC: four distinct charge states representing 00, 01, 10, 11 (two bits).
• TLC: eight distinct charge states representing the eight possible combinations of three bits.
• QLC: sixteen distinct charge states representing the sixteen possible combinations of four bits.
• PLC: thirty-two distinct charge states representing the thirty-two possible combinations of five bits.

The challenge with higher-density cells is that the charge differences between adjacent states get very small, making the cells more sensitive to disturbances and harder to read accurately.

ECC: error correction at the cell level

Because NAND cells have a non-trivial probability of returning incorrect bits (especially as cells wear), every NAND read goes through Error Correction Code (ECC) at the controller. The Cai et al. arXiv 2017 reliability paper captures the central tension: “the raw bit error rate eventually exceeds the maximum number of errors that can be corrected by ECC, at which point data loss occurs.”³ Modern SSDs use sophisticated ECC algorithms (typically LDPC codes) that can correct hundreds of errors per page; older drives used simpler BCH codes with lower correction capability.

The choice of NAND cell type shapes nearly every characteristic of an SSD: capacity per dollar, write speed, endurance, error rates, retention. Higher-density cells are cheaper but worse on most other dimensions.

Cell type comparison

Type	Bits/cell	P/E cycles	Cost	Common use
SLC	1	~100,000	Highest	Enterprise, industrial, embedded
MLC	2	~3,000-10,000	High	Older consumer SSDs, performance enterprise
eMLC	2	~10,000-30,000	Higher than MLC	Enterprise (binned MLC for higher endurance)
TLC	3	~1,000-3,000	Moderate	Most consumer SSDs (mainstream)
QLC	4	~100-1,000	Lower	Read-heavy consumer, archival, large-capacity
PLC	5	~50-300 (estimated)	Lowest	Emerging; not yet mainstream

SLC: the gold standard for reliability

Single-Level Cell NAND stores one bit per cell with two well-separated charge states. This gives SLC the highest endurance, fastest write speed, and lowest error rates of any NAND type, but at substantially higher cost per gigabyte. SLC is essentially limited to enterprise drives, industrial applications, and embedded systems where reliability matters more than cost. Most consumer-facing SLC use is now in cache form: SSD controllers may use a portion of TLC NAND in pseudo-SLC mode (only two charge states used) to provide a fast write buffer.

MLC: the legacy mainstream

Multi-Level Cell NAND stores two bits per cell with four charge states. MLC dominated consumer SSDs from approximately 2008 through the mid-2010s; it offered a workable balance of cost, performance, and endurance for general use. Modern consumer SSDs have largely transitioned away from MLC to TLC; MLC remains primarily in enterprise drives where additional endurance is valued.

TLC: current mainstream

Triple-Level Cell NAND stores three bits per cell with eight charge states. TLC dominates current consumer SSDs because it offers the best capacity-per-dollar at acceptable performance and endurance levels. The 8-state encoding is sensitive enough that TLC requires sophisticated ECC and read-retry strategies to maintain reliability over the drive’s life.

QLC: capacity-optimized consumer storage

Quad-Level Cell NAND stores four bits per cell with sixteen charge states. The endurance is substantially lower than TLC (often 10x lower P/E cycles), and write speeds are slower because the controller has to be more precise about charge placement. QLC works well for read-heavy workloads (large media libraries, archival storage, devices that mostly read existing data) but suffers in write-intensive use. Most large-capacity consumer SSDs (4 TB and above) use QLC because the cost savings dominate.

PLC and beyond: density-pushing emerging tech

Penta-Level Cell NAND with five bits per cell is in development by major manufacturers but hasn’t reached mainstream consumer products. The challenges scale with bits-per-cell: 32 distinct charge states require very precise charge placement and very sensitive read circuits, and the resulting cells have much shorter retention and lower endurance than QLC. PLC’s likely future is in archival and cold-storage roles where data is written once and read rarely.

NAND cells fail in several distinct ways. Understanding the failure modes explains why NAND has finite life and why some failure scenarios are recoverable while others aren’t.⁴

Wear-out from program/erase cycles

Every program (write) and erase operation drives electrons through the thin oxide layer that surrounds the floating gate. The Cai et al. research captures the central wear mechanism: each P/E cycle damages the oxide slightly, and the damage accumulates over cycles. The Nexus Industrial Memory documentation summarizes the eventual outcome: cells become unable to reliably hold their programmed charge, the raw bit error rate rises, and eventually exceeds what ECC can correct. At that point, data loss occurs.

Retention errors

The eProvided NAND flash documentation describes a key failure mode: “Common NAND failures include retention errors caused by charge leakage over time, which is often exacerbated by high temperatures or oxide degradation.” The trapped charge on the floating gate gradually leaks away even without active use; the cell’s threshold voltage drifts, and reads eventually return wrong values. Retention loss accelerates with temperature and with wear; aged cells stored at high temperatures lose data fastest. The JEDEC consumer SSD retention specification is typically 12 months at 30°C; cells significantly past their wear life or stored at high temperatures may fail retention much sooner.

Read disturb

Reading a NAND page applies a small voltage to nearby cells in the same block, slightly altering their stored charge. The cumulative effect of many reads to a block can shift the threshold voltages of other cells in that block enough that they read incorrectly. Read disturb is the reason SSDs sometimes proactively rewrite “cold” blocks that have been read many times: the controller refreshes the block’s contents to restore the original charge levels before they degrade beyond ECC’s ability to correct.

Program disturb

Writing one cell can slightly affect adjacent cells, both in the same word line and in adjacent word lines. The effect is small per write but accumulates over many writes to neighbors. Modern NAND controllers use various techniques to mitigate program disturb: optimized programming sequences, careful voltage profiles, and ECC strong enough to correct the resulting errors.

Cell-to-cell interference

The Cai et al. research identifies cell-to-cell interference as a major reliability factor: charge in one cell electrically influences neighboring cells, creating crosstalk that increases error rates. Modern NAND designs include various interference-mitigation techniques (encoding schemes that minimize problematic patterns, programming order optimizations) but the basic phenomenon remains a source of read errors.

Catastrophic failures

Beyond gradual wear-out, NAND can fail catastrophically:

• Manufacturing defects: some cells fail right out of the factory; modern NAND ships with substantial spare cells to compensate.
• Physical damage: dropped devices, water damage, impacts can crack NAND chip packages or break wirebonds.
• Electrical damage: overvoltage events can destroy NAND chips along with the controller.
• Heat damage: sustained operation above rated temperatures damages the oxide layer.

NAND data recovery is a substantially different discipline from HDD recovery. The mechanisms, tools, and success patterns reflect NAND’s unique architecture.⁵

Software-based recovery

For NAND devices that are still functional (the device powers on, the controller works, the file system has logical issues), software-based recovery works similarly to HDD recovery. The Nexus Industrial Memory documentation captures the approach: “Software-Based Recovery: Involves using specialised software tools designed to scan the NAND flash memory and recover readable data.” The recovery tool reads through the device’s normal interface, scans for file system structures and signatures, and reconstructs files. This handles accidental deletion, file system corruption, and many logical failures.

Firmware repair

The Nexus documentation describes a middle category of recovery: firmware corruption. “Sometimes, inaccessibility issues arise due to corrupted NAND flash controller firmware. Updating or re-flashing the firmware can restore access to stored data if the hardware remains intact.” This applies when the NAND cells themselves are healthy but the controller’s firmware has been damaged by a power event or other anomaly. Specialized tools can rewrite the firmware, restoring controller function and access to the underlying NAND data.

Chip-off recovery

For NAND devices that are physically damaged or have failed controllers, the path is chip-off recovery: the NAND chips are physically desoldered from the device’s circuit board and read directly using specialized hardware that bypasses the original controller. The eProvided NAND flash recovery documentation describes the workflow: “When standard access fails because of hardware damage or corruption, our engineers extract raw data from the NAND memory. We then reconstruct the original file system outside the device.” Chip-off can succeed even when the device won’t power on; recovery doesn’t depend on the operating system or motherboard.

The reconstruction challenge

Raw NAND data extracted via chip-off isn’t directly usable. Multiple layers of transformation between the raw flash content and the user’s logical data must be reversed:

• Wear leveling: the controller’s mapping table determines which physical NAND blocks correspond to which logical sectors. Without that mapping, the raw data is scrambled.
• Encryption: many modern devices encrypt all NAND content at the controller level. Recovery requires the encryption keys (often stored in the controller; if the controller is destroyed, the keys may be unrecoverable).
• Scrambling: NAND controllers apply data scrambling/whitening to avoid patterns that could cause increased error rates. The descrambling algorithm has to be reversed.
• ECC removal: raw NAND pages contain both user data and ECC parity. The ECC has to be applied to correct any errors and then stripped to leave clean user data.
• Multi-plane interleaving: data is often striped across multiple planes/dies for parallelism; the stripe pattern has to be reconstructed.

Advanced recovery techniques

The arXiv 2018 retention error research describes specific techniques:

• Read Reference Optimization (ROR): adjusts the read voltages used to determine bit values, compensating for charge that’s leaked away. Can extend flash lifetime by 64% and reduce error correction latency by 10.1%.
• Retention Failure Recovery (RFR): identifies and probabilistically corrects flash cells with retention errors. Reduces RBER by 50%, doubling effective error correction capability.

These techniques are increasingly being integrated into recovery workflows alongside more traditional approaches.

AI-assisted error correction

The eProvided NAND chip technology documentation notes a 2025 development: “AI tools for SSD data recovery use neural networks to interpret complex error patterns that traditional ECC struggles with, especially in high-density 3D NAND and QLC drives.” Neural networks trained on NAND error patterns can sometimes recover data from chips where conventional ECC has failed; the technique is most useful for high-density NAND where error patterns are complex.

Recovery success rates

The eProvided documentation cites a 95% success rate for NAND chip-off recovery. The favorable outcome depends on the specific failure mode: cases where the NAND itself is healthy but the controller has failed are highly recoverable; cases where many NAND cells have failed catastrophically have substantially lower success rates; cases with hardware encryption keys destroyed have nearly zero recovery prospects without the keys.